MAPS - Optimization

Optimization

Three areas of optimization are of interest. These are discussed in the orange box on the right side of the poster.

RF Band Selection

Small changes in phase are difficult to detect. Therefore, l needs to be small enough that a measurable change in distance results in a detectable phase shift. The commercially free 2.4GHz band is ideal. Many components are available and the wavelength is about .125m, so that one degree of phase shift equals .35mm. In addition, many new components are available for wireless networking in the 2.4GHz range. These components are easily adapted to our needs.

Phase Detector Design

The phase detector must have no amplitude dependence. As previously discussed, the design uses logarithmic amplifiers to convert both inputs into square waves of equal amplitude. This results in a detection based entirely on zero crossings. This is reprinted here for emphasis. This is a very critical part of the design.

Phase Locked Loop Optimization

Noise can vary the sine wave's phase, frequency and amplitude. All of these can contribute to fake zero crossings (some inevitable false readings can be filtered out in software if the signal to noise ratio is large). The system's PLL ([P]hase [L]ocked [L]oop) is the primary determinant of signal integrity. A PLL is needed to generate a stable signal at frequencies higher than those able to be generated by crystal osciallators. See wireless.national.com for a good discussion of PLLs.

There is a tradeoff in the PLL's loop filter between lock time (time to change channels), reference spur levels (the size of frequency-spectrum spurs that appear a distance away from the center frequency equal to the reference frequency*), number of channels (the bandwidth divided by the reference frequency), RMS phase noise, and the high order capacitor of the loop filter (must be kept smaller than the VCO's input capacitance or the two will add in parallel and distort the loop filter). Our PLL's loop filter is optimized to minimize RMS phase noise and obtain the lowest reference spurs possible while keeping the high order capacitor well above the VCO's input capacitance. The reference frequency is also chosen to be as large as possible to minimize reference spurs near the center frequency. Since the device does not need many channels nor need to switch channels, there is no downside to these optimizations.

*Crash course in PLLs: A PLL works by frequency dividing the output of a VCO ([V]oltage [C]ontrolled [O]scillator) down to some reference frequency and comparing it to a crystal oscillator's output similarly divided down. It generates corrective pulses to the VCO based on the difference in phase between the two (due to drift in the VCO's frequency). The loop filter low pass filters the corrective pulses.